1. Field of the Invention
The present invention relates to a method for fabricating a connector or an interposer, more particularly, to a method for fabricating a connector or an interposer that can decrease the consumption of gold by using positive-type photoresist.
2. Description of the Prior Art
Multi-functional and miniature electronic products have become a trend in electronic product development. In practice, each function generally must be realized in an independent chip. In other words, multi-function applications require multiple-chip solutions. However, if connections between independent chips are formed in a printed circuit board (PCB), a size of an electronic product inevitably grows. In order to improve on the problem, the integration of system in a package (SIP) therefore prevails. The main idea of the SIP is to set a plurality of chips that form a multi-function application on an interposer, such that connections between each of the plurality of chips occur across the interposer. Furthermore, the aforementioned chips and the interposer are packaged together to form a system package structure, and chips are electrically connected to one another through a conductive pattern inside the micro interposer. Furthermore, the system package structure is then bonded onto a printed circuit board via a plurality of conductive bumps or different types of leads to form a complete electrical system with other active electrical components or passive electrical components to effectively enable the operation in a variety of electronic products.
Current commercial interposer usually includes a substrate having a via penetrating through the two opposite surfaces of the substrate, and a connection component for external connecting the chip or other active or passive electronic components. It is noted that a gold layer is usually coated on the contacting area which is used for connecting the interposer to the chips or other active or passive electronic components, so as to increase the electrical conductivity or wear resistance of the connection component relatively to the chips or other active or passive electronic components.
In manufacture, the gold is selectively formed on the connection component by using a negative-type photoresist in conventional arts. However, by using the negative-type photoresist, due to the 3D obstruction of the connection component, a portion of the photoresist on the connection component, the substrate and the interior surface of the via are not exposed to light. After the development process, this portion of photoresist is stripped away. In the subsequent plating process, the gold is widely plated on these non-functional areas which are not subjected to light exposure. It therefore leads to more gold consumption in conventional arts because of the great areas of gold plating on the connection component. Moreover, when using the negative-type photoresist in conventional arts, the exposure and development processes should be carried out respectively upon the two opposite surfaces of the interposer. The use of two exposure and development processes renders the plating process more complicated and thus increases the costs and production time.
Accordingly, conventional method that uses the negative-type photoresist for plating the gold not only causes the waste of gold, but also requires two exposure processes to complete the gold plating process on the interposer.